1. Field of the Invention
The present invention relates to an advanced control method for use in an information processing apparatus, and in particular, to an advanced control method in an information processing apparatus employing a pipeline control method in which even when a conditional branch instruction is supplied to a pipeline of the apparatus, an advanced control is achieved to efficiently continue the instruction processing.
2. Description of Related Art
In the conventional information processing apparatus, to execute instruction processing at high speed, there have been generally adopted a pipeline control and an advanced control when executing instructions. In such an apparatus, when a branch instruction is processed, a processing flow of the advanced control is disturbed and hence the processing efficiency may possibly be reduced in some cases.
FIG. 3 is a block diagram showing the primary portion of the conventional information processing apparatus employing a pipeline control. The apparatus of FIG. 3 includes an instruction register 31, an address computing circuit 32, a memory 33, an arithmetic unit 34, a register (GCC) 35 for storing therein a condition code resultant from a computation, an advanced control condition code generating circuit 36, a selector 37, a condition code storing register (ICC) 38, a condition comparator 39, an instruction decoder 40, and an instruction control circuit 41.
In operation, upon receiving an instruction from the instruction register 31, the circuit 32 executes an address computation if the computation is necessary for the received instruction. Otherwise, for example, for an instruction of an operation between registers, the circuit 32 conducts the operation. Data read from the memory 33 for the instruction is supplied to the arithmetic unit 34 and then the data is subjected to the operation. A condition code representing an operation result from the unit 34 is stored in the GCC 35. The condition code (CC) generator circuit 36 checks the operation result from the circuit 32 and the data from the memory 33 to attain a condition code for an advanced control. The advanced control CC thus obtained is fed to the selector 37. The selector 37 selects either one of the received CCs. The CC selected by the selector 37 is loaded in the ICC 38.
The instruction from the instruction register 31 is also supplied to the instruction decoder 40 in addition to the address computing circuit 32. The instruction decoder 40 decodes an instruction of the instruction register 31. Control information of a condition judgement of the decode instruction is fed to the condition comparator 39. The circuit 39 judges, based on the control information, the condition code stored in the ICC 38 to determine whether the conditional branch instruction is successful or not. A judge signal of the branch success or failure is transmitted from the circuit 39 to the instruction control circuit 41. The circuit 41 determines, according to the judge signal, the next instruction to be loaded in the instruction register 31.
FIG. 4 is a signal timing chart of a pipeline control flow for explaining the operation of the conventional information processing apparatus.
In FIG. 4, the upper-most horizontal axis stands for sequential execution cycles 1 to 14 in the pipeline control. In an advanced control processing of a sequence of instructions by a pipeline control of this example, a sequence of instructions, i.e., an instruction 1, a conditional branch instruction 2, an instruction 3, a conditional branch instruction 4, an instruction 5, and instructions 6 to 10 are assumed to be processed. In the example of FIG. 4, the instruction 1 is an instruction for which an advanced control CC cannot be attained, whereas, the instruction 3 following the instruction 2 is an instruction for which an advanced control CC can be obtained. After the instruction 4, the instructions 5 to 9 are executed. The instruction 10 is a branch destination instruction and is processed as a prefetch instruction
The instruction 1 is supplied to the pipeline stage in cycle 1; thereafter, an operation of the instruction 1 is executed in cycle 5. According to a result of the operation, a CC resultant from the operation of the instruction 1 is set to the GCC 35; moreover, the CC is then transferred from the GCC 35 to the ICC 38 in cycle 7.
The branch instruction 2 is delivered to the pipeline stage in cycle 2, namely, with a delay of one cycle relative to the instruction 1. An address computation is conducted for the branch instruction 2. In cycle 6, the branch destination instruction is read from the memory 33. Subsequently, in cycle 7, a value of the CC established by the operation of the instruction 1 is referenced such that a condition judgement is conducted by the condition comparator circuit 39. Whether or not the next instruction to be executed is an instruction succeeding the branch instruction 2, i.e., the instruction 3, or is to be modified to a prefetch instruction of a branch destination instruction is decided by the instruction control circuit 41.
In consideration of a case where the branch attempt by the branch instruction 2 results in a failure, there is adopted a method in which the instruction 3 and the instructions subsequent thereto are sequentially supplied to the pipeline stage. Consequently, the instruction 3 is delivered to the pipeline stage in cycle 3. An advanced control CC of the instruction 3 is attained by an advanced control in cycle 6. However, in cycle 6, the advanced control CC conflicts with the CC of the instruction 1 loaded in the GCC 35 and hence cannot be set to the ICC 38. Consequently, the CC of the instruction 3 is attained as a CC of the operation result in cycle 8 and the obtained CC is set to the GCC 35 so as to be transferred therefrom to the ICC 38 in cycle 9.
The branch instruction 4 is fed to the pipeline stage in cycle 4. In cycle 9, the value of CC of the instruction 3 is referenced and the condition judgement is conducted by the condition comparator 39. As a result, whether an instruction to be subsequently executed is an instruction following the instruction 4, i.e., the instruction 5 or is to be changed to a prefetch instruction of the branch destination, i.e., the instruction 10 is judged by the instruction control circuit 41. If the branch is successful, the prefetch instruction is supplied to the pipeline stage in cycle 10. Namely, the delivery of the prefetch instruction is achieved with a delay of six cycles relative to the delivery of the branch instruction 4 to the pipeline stage. On the other hand, if the branch attempt fails, the instruction 4 and the instructions subsequent thereto are executed. In consideration of a failure of the branch, there is employed a method in which the instruction 4 and the instructions subsequent thereto are sequentially supplied to the pipeline stage. Consequently, no particular delay takes place. In the case where the branch is successfully conducted, these instructions beforehand loaded in the pipeline stage are invalidated and hence there does not occur any adverse result.
A known example related to the advanced control of this kind has been described in the JP-A-63-231672.
In the conventional information processing apparatus employing the pipeline control, consideration has not been given to a method of controlling the ICC when a conflict occurs between the advanced control CC and the CC attained from the computation. Resultantly, the determination of the CC of the subsequent instruction is delayed in the ICC. Consequently, there arise problems of the delay in the judgement of the conditional branch instruction for the branch success or failure and the delay in such operations as decoding and execution of the prefetch instruction of the branch destination.